Research and Design of Base Station RF Card Clock Tree

Due to the occasional need to support RF cards in remote radio heads, most RF cards use a link-to-base station recovery clock as the input clock. The quality of these single-input clocks is poor and may require significant jitter to be cleared in order to efficiently generate other clocks on the RF card.

Therefore, the core of the RF card clock tree must be a jitter attenuator with a programmable output frequency. The rest of this article will discuss performance attributes and the reasons for these performance attributes, as well as other clock tree requirements.

RF Card Architecture Considerations

Today, many of the operations performed by most base station RF card designs require the establishment or termination of protocol signals such as LTE or multi-carrier GSM in the digital domain. This is a simpler way to handle error correction, channel mapping, and digitally splitting I, Q data streams. The complex data stream of this composite signal also requires very careful filtering/signal processing in both the transmit and receive directions. Doing this in the digital domain avoids the cost of matching precision component values.

Despite the variety of digital operations, at some point the signal must be modulated into a carrier that can travel from 824 MHz to 2.62 GHz and transmitted as an analog signal. Address multi-channel protocols for most base station architectures include single-stage analog conversion methods used by LTE, WiMax, and multi-carrier GSM, as shown in Figure 1.


Figure 1 Typical LTE RF card architecture

At the transmitting end, except for the first modulation, each subcarrier is combined into one digital stream. This baseband signal is then converted by the DAC to a phase shifting offset analog I, Q data stream, which is then upconverted to a transmission frequency by a quadrature analog mixer. Variable and fixed gain amplifiers and duplex filters are used to increase the useful signal along the path to the desired intensity of its transmission band, while adding only a small amount of noise and distortion while minimizing energy outside the transmission band to prevent Interference to other RF channels.

At the receiving end, the RF signal is typically amplified, filtered, and then converted to a lower intermediate frequency (IF) in the 75-250 MHz range by a mixer, in which the RF signal passes through a variable amount, filtered, and finally by a The pipelined ADC is further amplified by sampling according to the Nyquist criterion. The downconversion and demodulation of the subcarriers are then processed in the digital domain. The goal of the receiver is to complete this signal conditioning before the ADC gets the minimum additional noise and intermodulation distortion, while avoiding exceeding the maximum range of the ADC.

RF card architects prefer to integrate the clock tree as much as possible. Not only for the above reasons, but because each clock tree component has its own jitter contribution, which can push the clock signal out of specification. This integration not only produces RF and IF-modulated clocks, but also generates sample clocks for ADCs and DACs and other digital component clocks such as CPUs, ASICs, and FPGAs.

These digital components typically have a wider range of clocks than clocks that involve RF signal paths; periodic jitter is the most common major problem. When these clocks are generated on the same chip with these more sensitive clocks, two problems arise. First, the digital clock signal is rarely an integral multiple of the RF card input clock signal, so it must be generated using fractional feedback or fractional output crossover techniques. However, these two techniques introduce significant parasitic content into the clock chip and clock output. Second, the digital clock chip (or any parasitic content generated during generation) can be easily filtered out by approaching the RF, IF, or sampling frequency, so it must be avoided. Frequency components outside of these response regions may reduce the signal-to-noise ratio, whether as broadband noise (if there is no filtering) or by aliasing into the critical frequency range.

Frequency effects of mixers, ADCs, and DACs

A mixer is an analog component used to convert high frequency signals to low frequency signals. In most base station RF card designs, the mixer converts the signal from RF to IF or from baseband to RF. The main concern of clock tree design is the frequency aliasing problem. These frequencies affect each other when multiple frequencies pass through a nonlinear device. These interactions are called intermodulation products. The function of the mixer is to obtain two input frequencies and generate an output frequency, either the sum of the two frequencies (upconversion) or the difference between the two frequencies (downconversion).

Today's RF cards are designed to recover signals of multi-carrier nature. Therefore, the ideal signal is not a useful signal for a single audio line, but rather a full range of audio lines that are evenly distributed throughout the response band. These lines represent the various channels that are recovered. Unfortunately, because this multi-carrier signal runs through nonlinear components such as mixers, each channel here will be intermodulated with each other. The neat spacing of the channels will cause the odd order product to fall almost entirely on top of the recovered channel. The filter placed in front of the mixer will be used to attenuate the noise, which will help achieve even order products. Filters placed after the mixer will eliminate intermodulation products that fall outside the response band, but nothing can be done for in-band odd-order products because they fall too close to the useful signal.

Although the bandpass filter placed after the mixer can eliminate the unwanted silencer, this is not bad, but any jitter on the sample clock will turn the clean line into a skirt, as shown in Figure 2. Show. The tail from the edge of each undesired product will have some effect on the passband of the filter, which is called broadband noise. Any clock (or ADC or DAC) generated by the mixer must have an extremely low noise floor to reduce its wideband noise.


Figure 2 The effect of mixing with each other

Unwanted signals are referred to as "interference" or "blockers," and the input to the mixer will have an effect on the specification of the clock signal. They may contain other signals received through the antenna, or system internal signals coupled into the receive signal path. Although the "blocking" that separates the wanted signal from the wide frequency can be significantly suppressed by the pre-filter, the frequency close to the useful signal will still pass. Furthermore, in protocols like LTE, the wanted signal has a lower average power, and even if it is attenuated by a filter, it may still contain enough energy to compete with the useful signal.

This is why the edge of the clock phase noise entering the mixer must be as narrow as possible. The propagation of phase noise that is “mixed” on each other must be kept to a minimum. One of the main challenges in RF card design is to choose the frequency of the card, with a view to maximizing the separation of "blocking" and its intermodulation products from the frequency of the wanted signal.

Other effects of ADC jitter

Since the ADC is a sampled data system rather than a fully linear conversion, between the useful input signal, the unwanted ("blocking") signal, and the sampling clock, they will all be affected by the same intermodulation.

However, there is another way to drive the ADC sampling clock specifications. This is the aperture dithering effect, as shown in Figure 3.


Figure 3 ADC aperture jitter

The basic concept is that any time-indetermined sample can be converted to the uncertainty of the sample amplitude by trigonometry. Uncertainty in amplitude can result in a decrease in the signal-to-noise ratio of the ADC. Once the frequency of the input signal is known, the RMS jitter target can be determined as the ideal signal to noise ratio of the ADC. Once the target is reached, the inherent jitter of the clock tree within the ADC can be decomposed to determine the target RMS jitter specification for the sample clock.

The effect of clock jitter on the DAC

A digital-to-analog converter (DAC) for the transmit path converts a digitally represented baseband signal into an analog representation of the baseband signal for subsequent conversion to RF frequency and amplification to the desired transmit power. RF card designers will focus on the frequency planning of the fixed card to ensure that the sampling frequency of the DAC does not overlap with the critical band at the receiving card end. This is important because the DAC is affected by frequency-generated images from two potential mechanisms.

The first mechanism is the same as that occurring in the ADC and mixer. The sampling clock's convolution (fLO) and input signal (fIN) are generated at frequencies of N·fLO+M·fIN. This convolution result comes from the nonlinearity of the converter. The effect on the requirements of the sample clock jitter is similar to that of the ADC.

The second mechanism is the inevitable result of most DACs working. As shown in Figure 4, at each sample clock edge, the output of the DAC will soon switch to a new voltage level to represent the digital sample value. This value will be held until the next sampled clock edge. The output only matches the desired waveform for each sample clock.


Figure 4 Comparison of DAC output and ideal output

This will result in the introduction of error energy. In addition, most DACs will be affected by some sort of clock feedthrough, causing further spikes in N·fLO. For this reason, the sampling clock frequency tends to be much higher than the Nyquist requirement, so that the feedthrough spike far exceeds the response frequency and can therefore be easily filtered.

The DAC output waveform will eliminate as much of this unwanted frequency as possible through the analog reconstruction filter. If the clock jitter and phase noise edges are well controlled, the filter design will be easier and the implementation cost will be lower. In addition to the specific bit noise level requirements of the sample clock at specific offset conditions, there is also a specification for integrating RMS jitter over a range of frequencies. This is due to the distortion of the ideal output waveform due to clock jitter. This will reduce the total harmonic distortion (THD) or signal-to-noise plus distortion ratio (SINAD) of the DAC; it must be kept within specification to prevent degradation of the RF card's error vector magnitude (EVM). At the transmitting end, lower clock jitter can directly make the EVM better, or it can be used to relax the crest factor/peak-to-average power ratio reduction circuit design constraints.

Phase adjustment requirements in the RF card

In addition to basic voice and data transmission services, many mobile users require additional services. For example, a set of signal transmission towers is used to achieve precise positioning of the user by triangulation. Optimal positioning is achieved by RF trigonometry when all antennas transmit and receive phase calibration signals to each other. Some such services require independent base stations to operate between them at less than 50 ns. The budget for a radio card is: how many phase differences it may introduce relative to other wireless cards in the same system. This is another reason why each RF card uses an internal clock input signal to generate all of its internal frequencies. It ensures that the phase calibration of all clocks on the card has at least one common starting point.

to sum up

RF cards require a clock that is often noisy to generate various clocks. Very few of these output clocks are integer relationships to the input clock. All clocks must be aware of their total amount of noise to prevent noise from coupling to critical circuits. Clocks specifically for mixing functions include ADCs and DACs, which have strict specifications for RMS jitter and noise edges to avoid blocking signals in the RF signal path.

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